Date of Award


Degree Type


Degree Name

Doctor of Philosophy (PhD)


Electrical and Computer Engineering


Professor Radek M. Biernacki


This thesis contributes to computer oriented techniques for nominal and statistical design of analog circuits. Innovative software concepts aiming at shortening the design time are described. The problem of interfacing circuit CAD tools for design automation is addressed.

The concept of response modeling is reviewed. Benefits and limitations of utilizing response modeling in nominal and statistical design are discussed. A multilevel approach to response modeling offering additional CPU time savings is introduced. Challenges associated with employing grid- based simulators with discrete parameters in the design process are addressed.

A highly efficient quadratic interpolation technique is reviewed, extended and used for response modeling. Dedicated data base techniques and an effective parallel processing scheme are developed to complement the quadratic interpolation and further increase the CPU time savings.

Flexible circuit optimization where a powerful optimization system can interact with various external simulators is addressed. An interface capable of integrating such an optimization system with external and independent simulators is developed. Approaches to automating the process of preparing the external simulator input and capturing its output are described.

The novel Space Mapping approach to optimization with CPU intensive simulators is reviewed.

The theoretical and software developments are implemented and tested on several advanced and industrially relevant circuit problems. Results of designs utilizing circuit theory-based and electromagnetic simulators are reported.

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