Date of Award
Master of Applied Science (MASc)
Electrical and Computer Engineering
T. H. Szymanski
Crossbar switches are fundamental building blocks of digital networks, such as the
Internet. An Input-Queued (IQ) switch with a set of queues at the input side is the most widely used crossbar switch due to the scalability and low design complexity. While IQ switches are used in commercial routers, the schedulers are relatively complex. An alternative switch design is to insert a FIFO queue in each crosspoint of an IQ switch. This architecture is named the Combined Input and Crosspoint Queued switch, denoted as CIXQ. The use of crosspoint queues simplifies the scheduling of traffic through the switch, at the cost of adding N2 FIFO queues to the switch fabric.
In recent years, considerable research has been made to study the capability and
flexibility of the CIXQ switch over high-speed networks. In this thesis, we will review the CIXQ switch by focusing on the switching performance, design implementation and
power consumption. The switching performance is first evaluated using MATLAB. The
analysis results show that the CIXQ switch with a simple Round Robin scheduling can
achieve a high performance under various traffic patterns. In an attempt to analyze the
power consumption, a CIXQ switch is then implemented in VHDL based on a broadcastand-select architecture and a DEMUX-MUX architecture. The designs are tested and simulated on Altera Cyclone II FPGAs. The simulation results illustrate that the switches are operational correctly as specified in Chapter 4. As power has become a critical design issue, a power analysis for IQ and CIXQ switches is finally presented. Analytic power models for the switches in an FPGA environment are developed. As the major contribution of this thesis, we are the first to develop power models for the CIXQ switch. The power models allow the designers to explore the power efficiency of various crossbar switches in the early stages of design process. The verification indicates that the power models are quite accurate with an average error of less than 10%. The analysis also shows that a CIXQ switch with N 2 crosspoint queues consumes about three times as much power as the IQ switch for modest size switches (4x4, 8x8, and 16xl6) in an FPGA environment.
In conclusion, we present an analysis of the design implementation and power
consumption of the CIXQ switch. The discussions illustrate a fact that the CIXQ switch
with a FIFO queue in each crosspoint increases the cost and hardware complexity even
though it will simplify the scheduling problem. The designers must analyze this trade-off
when making architectural design decisions.
Wang, Jian, "A POWER ANALYSIS OF THE COMBINED INPUT AND CROSSPOINT QUEUED SWITCH" (2009). Open Access Dissertations and Theses. Paper 4082.
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